1. Field
Embodiments of the present invention relate generally to a memory device including a refresh controller.
2. Description of the Related Art
A memory cell of a memory device includes a transistor serving as a switch for controlling the flow of charges in and out of a capacitor which stores the charges. The charges of course represent data and, more specifically, according to the level of the voltage of the capacitor, data may be high logic (logic 1) or low logic (logic 0).
Retaining the data requires maintaining the charges in the capacitor. Because, charges may leak due to the PN junction of a MOS transistor, the data may be lost. Hence, to prevent data loss, the charges are read before the data is lost, and recharged periodically a process generally referred to as a refresh operation.
Typically, a refresh operation is performed whenever a refresh command is inputted to a memory from a memory controller. Considering the data retention time of the memory, the memory controller inputs the refresh command to the memory at each set time. The data retention time indicates a time during which data of a memory cell can be retained without a refresh operation. Since memory cells included in a memory device are designed to have a data retention time equal to or more than a reference retention time, the interval between refresh operations may be determined in consideration of the reference retention time.
However, when the charge of a certain memory cell is influenced by an active-precharge operation of a word line adjacent to a word line to which the corresponding memory cell is coupled, the data of the memory cell may be deteriorated within a shorter time than the refresh interval. Such a phenomenon is referred to as a row hammering effect.
FIG. 1 is a diagram illustrating a part of a cell array included in a memory device, in order to describe the row hammer effect. In FIG. 1, BL represents a bit line.
Referring to FIG. 1, WLK−1, WLK and WLK+1 represent three adjacent word lines which are arranged in parallel within the cell array. WLK with ATTACK_ACT represents a word line of which the active count or frequency is high or the active time is long, and WLK−1 and WLK+1 represent word lines adjacent to the word line WLK. CELL_K−1, CELL_K and CELL_K+1 represent memory cells coupled to the word lines WLK−1, WLK and WLK+1, respectively. The memory cells CELL_K−1, CELL_K and CELL_K+1 may include cell transistors TR_K−1, TR_K and TR_K+1 and cell capacitors CAP_K−1, CAP_K and CAP_K+1, respectively.
In FIG. 1, when the word line WLK is frequently activated or activated for a long time, the voltage of the word line WLK frequently toggles or is retained at a high voltage for a long time. Then, a coupling effect between the word line WLK and the word lines WLK−1 and WLK+1 may have an influence on data stored in the memory cells CELL_K−1 and CELL_K+1 coupled to the word lines WLK−1 and WLK+1. Such an influence can reduce the time during which the data stored in the memory cells can be retained and is generally known as the word line or row hammer effect.